Middle of the line (MOL) design is becoming more challenging in advanced technology nodes due to the cell size scaling and process capabilities. For the MOL local interconnect metals, due to track height scaling, there is less local routing resources for the drain and source contacts, as well as the gate contacts. This results in congestion at the MOL contact level and/or the lower wiring levels, e.g., M0 level.
For example, MOL architecture need two levels of contacts to connect gate to the first wiring level, e.g., M0 level. That results in more contact congestion. Also, congestion of the contacts occur when there is a need to use the M0 level to connect the source, drain and gate contacts for SRAM cross couple. In this situation, there may be a need to move VDD from the M0 layer to a higher wiring layer, e.g., M2 layer, and/or enable tighter M0 minimum area requirement or super via processes (e.g., a tall V0 directly connecting to the source/drain contacts).
Moreover, self-aligned gate contacts may be required to achieve the target area scaling in future technologies (i.e., 5 nm, 3 nm, etc. technology nodes). However, since self-aligned gate contacts do not short to gate structures, there is also a need to use the M0 layer to connect the source, drain and gate contacts for SRAM cross couple. This, in turn, causes further M0 congestion, and hence M0 level VDD in SRAM technologies may not be possible.